//???????:
//clk_4Hz: ??????(??)?????;
//clk_6MHz: ???????????????;
//speaker: ????????????,????????;
//high, med, low:????????????????,????????????

/*clk_6MHz?clk_4Hz????*/
module clk_6_4(clk_50MHz,clk_6MHz,clk_4Hz);
    input clk_50MHz;
    output clk_6MHz, clk_4Hz;
    wire clk_50MHz;
    reg clk_6MHz, clk_4Hz;
    //wire clk_6MHz, clk_4Hz;
    reg [2:0] counter1;
    reg [31:0] counter2;
    //reg  clk3,clk4;
always @(posedge clk_50MHz) 
  begin 
  if(counter1 == 4) begin   
    counter1 <= 3'b000;   
    //clk3 <= ~clk3;   
    clk_6MHz <= ~clk_6MHz ;   
  end 
  else 
  counter1  <= counter1 + 1;
  end
  //assign clk_6MHz = clk3;
always @(posedge clk_50MHz) 
  begin 
  if(counter2==6250000) begin   
  counter2 <= 3'b000;  
  //clk4 <=~clk4;   
  clk_4Hz <= ~clk_4Hz;   
  end 
  else 
  counter2  <= counter2+1;
  end
  //assign clk_4Hz = clk4;
endmodule

/*??????????*/
module liangzhu_fpga(clk_6MHz, clk_4Hz, speaker, high, med, low);
    input clk_6MHz, clk_4Hz;
    output speaker;
    output [3:0] high,med,low;
    reg [3:0] high,med,low;
    reg [13:0] divider,origin;
    reg [7:0] counter;
    reg speaker;
    wire carry;
    assign carry = (divider == 16383); //16383=11111111111111
always @(posedge clk_6MHz)
  begin 
  if(carry) 
  divider = origin;
  else 
  divider = divider + 1;
  end
always @(posedge carry)
  begin
  speaker = ~speaker; //2 ????????
  end
always @(posedge clk_4Hz)
  begin
  case({high,med,low}) //?????
  'b000000000011: origin = 7281;
  'b000000000101: origin = 8730;
  'b000000000110: origin = 9565;
  'b000000000111: origin = 10310;
  'b000000010000: origin = 10647;
  'b000000100000: origin = 11272;
  'b000000110000: origin = 11831;
  'b000001010000: origin = 12556;
  'b000001100000: origin = 12974;
  'b000100000000: origin = 13516;
  'b000000000000: origin = 16383;
  endcase
  end
always @(posedge clk_4Hz)
  begin
  if(counter == 63) 
  counter = 0; //??,???????
  else 
  counter = counter + 1;
  case(counter) //??
  0: {high,med,low}='b000000000011; //??"3"
  1: {high,med,low}='b000000000011; //??4 ?????
  2: {high,med,low}='b000000000011;
  3: {high,med,low}='b000000000011;
  4: {high,med,low}='b000000000101; //??"5"
  5: {high,med,low}='b000000000101; //?3 ?????
  6: {high,med,low}='b000000000101;
  7: {high,med,low}='b000000000110; //??"6"
  8: {high,med,low}='b000000010000; //??"1"
  9: {high,med,low}='b000000010000; //?3 ?????
  10: {high,med,low}='b000000010000;
  11: {high,med,low}='b000000100000; //??"2"
  12: {high,med,low}='b000000000110; //??"6"
  13: {high,med,low}='b000000010000;
  14: {high,med,low}='b000000000101;
  15: {high,med,low}='b000000000101;
  16: {high,med,low}='b000001010000; //??"5"
  17: {high,med,low}='b000001010000; //?3 ?????
  18: {high,med,low}='b000001010000;
  19: {high,med,low}='b000100000000; //??"1"
  20: {high,med,low}='b000001100000;
  21: {high,med,low}='b000001010000;
  22: {high,med,low}='b000000110000;
  23: {high,med,low}='b000001010000;
  24: {high,med,low}='b000000100000; //??"2"
  25: {high,med,low}='b000000100000; //??11 ?????
  26: {high,med,low}='b000000100000;
  27: {high,med,low}='b000000100000;
  28: {high,med,low}='b000000100000;
  29: {high,med,low}='b000000100000;
  30: {high,med,low}='b000000100000;
  31: {high,med,low}='b000000100000;
  32: {high,med,low}='b000000100000;
  33: {high,med,low}='b000000100000;
  34: {high,med,low}='b000000100000;
  35: {high,med,low}='b000000110000; //??"3"
  36: {high,med,low}='b000000000111; //??"7"
  37: {high,med,low}='b000000000111;
  38: {high,med,low}='b000000000110; //??"6"
  39: {high,med,low}='b000000000110;
  40: {high,med,low}='b000000000101; //??"5"
  41: {high,med,low}='b000000000101;
  42: {high,med,low}='b000000000101;
  43: {high,med,low}='b000000000110; //??"6"
  44: {high,med,low}='b000000010000; //??"1"
  45: {high,med,low}='b000000010000;
  46: {high,med,low}='b000000100000; //??"2"
  47: {high,med,low}='b000000100000;
  48: {high,med,low}='b000000000011; //??"3"
  49: {high,med,low}='b000000000011;
  50: {high,med,low}='b000000010000; //??"1"
  51: {high,med,low}='b000000010000;
  52: {high,med,low}='b000000000110;
  53: {high,med,low}='b000000000101; //??"5"
  54: {high,med,low}='b000000000110;
  55: {high,med,low}='b000000010000; //??"1"
  56: {high,med,low}='b000000000101; //??"5"
  57: {high,med,low}='b000000000101; //??8 ?????
  58: {high,med,low}='b000000000101;
  59: {high,med,low}='b000000000101;
  60: {high,med,low}='b000000000101;
  61: {high,med,low}='b000000000101;
  62: {high,med,low}='b000000000101;
  63: {high,med,low}='b000000000101;
  endcase
  end
endmodule

/*????????????????????,????????????????*/
module seg7(clk_4Hz, high, med, low, seg7_r, seg_r);          
    input clk_4Hz;                             
    input [3:0] high; 
    input [3:0] med;
    input [3:0] low;                                                   
    output [7:0] seg_r;
    output [7:0] seg7_r;
    wire [3:0] high; 
    wire [3:0] med;
    wire [3:0] low; 
    reg [7:0] seg_r;
    reg [7:0] seg7_r; 
always@(posedge clk_4Hz)
  begin
case({high,med,low}) 
  12'b000000000011: 
  begin 
  seg7_r <= 8'b11111110;
  seg_r <=8 'hb0; 
  end//??3
  12'b000000000101:
  begin 
  seg7_r <= 8'b11111110;
  seg_r<=8'h92; 
  end//??5
  12'b000000000110:
  begin 
  seg7_r <= 8'b11111110;
  seg_r<=8'h82; 
  end //??"6"
  12'b000000010000:
  begin 
  seg7_r <= 8'b11111101;
  seg_r<=8'hf9;
  end //??"1"
  12'b000000100000:
  begin 
  seg7_r <= 8'b11111101;
  seg_r<=8'ha4; 
  end//??"2"
  12'b000001010000:
  begin 
  seg7_r <= 8'b11111101;
  seg_r<=8'h92;
  end//??"5"
  12'b000100000000: 
  begin 
  seg7_r <= 8'b11111011;
  seg_r<=8'hf9; 
  end//??"1"
  12'b000000110000: 
  begin 
  seg7_r <= 8'b11111101;
  seg_r<=8'hb0; 
  end//??"3"
  12'b000000000111: 
  begin 
  seg7_r <= 8'b11111110;
  seg_r<=8'hf8; 
  end//??"7"
endcase
  end                               
endmodule
